No subject

~ # ethercat -p2 reg_read 0x500 -t uint16  <-- Read EEPROM config register
0x0000 0
~ # ethercat -p2 reg_write 0x500 1 -t uint16 <-- Set bit 0 in config regist=
er
~ # ethercat -p2 reg_read 0x500 -t uint16
0x0001 1                                     <-- Now the bit is set, the sl=
ave PDI can access the EEPROM

My slaves updates the object (0x1018) on a transition from INIT to PREOP

~ # ethercat sl
0  0:0  PREOP  +  PCM5.1 Power and Control Module
1  0:1  PREOP  +  PDM5.2 Power and Distributed Communication Module
2  0:2  PREOP  +  IOM5.1 Input and Output Module
~ # ethercat -p2 st init
~ # ethercat -p2 st preop
~ # ethercat -p2 reg_read 0x500 -t uint16  <-- Bit is not altered by the ma=
ster
0x0001 1
~ # ethercat -p2 upload 0x1018 4 -t uint32  <-- Read object 0x1018 subindex=
 4 - serial number
0x01020304 16909060                         <-- My slave serial number

I propose that the master by default allows the slaves to read the EEPROM f=
rom PDI side by setting this bit (register 0x500.0 =3D 1) when it is not us=
ed by the master.

Med venlig hilsen/Best regards/Viele Gr=FCssen

Frank Kjul Larsen
DEIF Wind Power Technology
SW Developer B.Sc.E.E.

Tel.:    +45 9614 8462

fkl at deif.com

---------------------------------------------------------------

DEIF A/S
Frisenborgvej 33
DK-7800 Skive

Tel.: +45 9614 9614=20
Fax:  +45 9614 9615

www.deifwindpower.com

DEIF Power and Marine you find at www.deif.com