<div dir="ltr"><div><div><div><div>Hello all,<br><br></div>I have problems configuring an EL6692 bridge module "sides" (primary & secondary) - when Etherlab is on the primary side, this side configures seemingly without problems. On secondary side, the aboslutely same configuration produces "invalid input configuration", and slave never goes to OP, stays at PREOP+ERROR. <br><br>Aside from error 0x001e, "invlaid input configuration". In some other tests with the same module, I also recall occasionally getting the error code 0x00f0 "Application Controller available" - anyone knows what this actually means?<br><br></div><div>This slave has about 0.5kB of programmable memory on both "sides" (primary/secondary), and it is possible to define various in/out PDO entries on both sides (SM2/SM3), which are then copied from one side to the other, depending on the direction. I have tested the module with the TwinCAT 3, and the configuration on both sides produces no error.<br></div><div><br></div><div>With Etherlab master, Test1 runs ok, on primary side. Test2, on the secondary side, does not appear to set any of the 2 new PDO entries, and slave finishes with ERROR flag. Test 3 also runs on secondary side, however it appears to manage to set the new PDO entries, but the slave also refuses to switch to OP, reports ERROR, just like Test2.<br><br></div><div>The problem is, I need to use this module with the Etherlab master connected to the secondary side, with a TwinCAT on the primary side, both having the same PDO entry config for SM2/SM3.<br><br></div><div>Below are some outputs, as well as the test program source. attached are 3 x debug 1 output logs for Tests 1, 2 and 3, and sdos.txt with the SDO list for EL6692.<br><br></div><div>What am I doing wrong?<br><br></div><div><br></div><div>Thanks in advance,<br></div><div>DMM<br></div><div><br><br><br></div><div>Test 1: Primary side <br>#define POS_6692 1<br></div><div>#define SM0SM1 0 // it also works with SM0SM1=1<br></div><div>Etherlab --> EK1100 --> EL6692 (as Slave 1, connected to primary side via EK1100, secondary side connected directly to TwinCAT)<br></div><div><br><div>Test 2: Secondary side<br></div><div>#define POS_6692 0<br><div>#define SM0SM1 0<br></div>Etherlab --> EL6692 (as Slave 0, connected directly to secondary side, primary side has EK1100 connected to TwinCAT, and EL6692 connected to EK1100)<br></div><div><br><div>Test 3: Secondary side<br></div><div>#define POS_6692 0<br><div>#define SM0SM1 1<br></div>Etherlab --> EL6692 (as Slave 0, connected the same way as in Test2)<br></div><br><br><br>-------------------------------------------<br></div><div>EL6692 PDOs before test programs, and after Test2:<br><br><font size="1"><span style="font-family:monospace,monospace">=== Master 0, Slave 1 ===<br>SM0: PhysAddr 0x1000, DefaultSize 256, ControlRegister 0x26, Enable 1<br>SM1: PhysAddr 0x1400, DefaultSize 256, ControlRegister 0x22, Enable 1<br>SM2: PhysAddr 0x1800, DefaultSize 0, ControlRegister 0x24, Enable 1<br> RxPDO 0x1600 "IO Outputs"<br>SM3: PhysAddr 0x1e00, DefaultSize 2, ControlRegister 0x20, Enable 1<br> TxPDO 0x1a01 "SYNC Inputs"<br> PDO entry 0x10f4:01, 2 bit, "Sync Mode"<br> PDO entry 0x0000:00, 6 bit, ""<br> PDO entry 0x0000:00, 3 bit, ""<br> PDO entry 0x1800:09, 1 bit, "TxPDO toggle"<br> PDO entry 0x1800:07, 1 bit, "TxPDO state"<br> PDO entry 0x10f4:0e, 1 bit, "Control value update toggle"<br> PDO entry 0x10f4:0f, 1 bit, "Timestamp update toggle"<br> PDO entry 0x10f4:10, 1 bit, "External device not connected"<br> TxPDO 0x1a00 "IO Inputs"</span></font><br><br><br></div><div>-------------------------------------------<br>EL6692 PDOs after Test1 and Test3 programs:<br><br></div><div><font size="1"><span style="font-family:monospace,monospace">=== Master 0, Slave 1 ===<br>SM0: PhysAddr 0x1000, DefaultSize 256, ControlRegister 0x26, Enable 1<br>SM1: PhysAddr 0x1400, DefaultSize 256, ControlRegister 0x22, Enable 1<br>SM2: PhysAddr 0x1800, DefaultSize 0, ControlRegister 0x24, Enable 1<br> RxPDO 0x1600 "RxPDO-Map"<br> PDO entry 0x6000:00, 8 bit, ""<br>SM3: PhysAddr 0x1e00, DefaultSize 2, ControlRegister 0x20, Enable 1<br> TxPDO 0x1a00 "TxPDO-Map"<br> PDO entry 0x7000:00, 8 bit, ""<br><br></span></font></div><div><br><br><br><br><br>-----------------------------------------------------------------------------------------------------------------------<br></div><div>Debug 1 log with Test1 results (primary side), when there is NO error, slave goes to OP (test1log.txt attached). Here are the last few lines:<br></div><div><font size="1"><span style="font-family:monospace,monospace"><br></span></font></div><font size="1"><span style="font-family:monospace,monospace">[91071.665432] EtherCAT DEBUG 0-1: SM2: Addr 0x1800, Size 1, Ctrl 0x24, En 1<br>[91071.665438] EtherCAT DEBUG 0-1: SM3: Addr 0x1E00, Size 1, Ctrl 0x20, En 1<br>[91071.685866] EtherCAT DEBUG 0 0:1: FMMU: LogAddr 0x00000000, Size 1, PhysAddr 0x1E00, SM3, Dir in<br>[91071.685875] EtherCAT DEBUG 0 0:1: FMMU: LogAddr 0x00000001, Size 1, PhysAddr 0x1800, SM2, Dir out<br>[91071.745132] EtherCAT DEBUG 0-1: Now in SAFEOP.<br>[91071.784871] EtherCAT DEBUG 0-1: Now in OP. Finished configuration.<br>[91071.805248] EtherCAT 0: Slave states on main device: OP.<br><br><br></span></font>-----------------------------------------------------------------------------------------------------------------------<br><div>Debug 2 log with Test2 results (secondary side, only SM2 and SM3 configured), when there is error, slave goes to
PREOP+ERROR (test2log.txt attached). Here are the last few lines:<br></div><div><font size="1"><span style="font-family:monospace,monospace"><br>[91662.071028] EtherCAT DEBUG 0: Requesting OP...<br>[91662.111186] EtherCAT DEBUG 0-0: Changing state from PREOP to OP.<br>[91662.111194] EtherCAT DEBUG 0-0: Configuring...<br>[91662.150327] EtherCAT DEBUG 0-0: Now in INIT.<br>[91662.150335] EtherCAT DEBUG 0-0: Clearing FMMU configurations...<br>[91662.170947] EtherCAT DEBUG 0-0: Clearing sync manager configurations...<br>[91662.190766] EtherCAT DEBUG 0-0: Clearing DC assignment...<br>[91662.211228] EtherCAT DEBUG 0-0: Configuring mailbox sync managers...<br>[91662.211238] EtherCAT DEBUG 0-0: SM0: Addr 0x1000, Size 256, Ctrl 0x26, En 1<br>[91662.211244] EtherCAT DEBUG 0-0: SM1: Addr 0x1400, Size 256, Ctrl 0x22, En 1<br>[91662.270654] EtherCAT DEBUG 0-0: Now in PREOP.<br>[91662.270665] EtherCAT DEBUG 0-0: SM2: Addr 0x1800, Size 0, Ctrl 0x24, En 0<br>[91662.270671] EtherCAT DEBUG 0-0: SM3: Addr 0x1E00, Size 2, Ctrl 0x20, En 1<br>[91662.330686] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).<br>[91662.351024] EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".<br>[91662.390698] EtherCAT 0-0: Acknowledged state PREOP.<br></span></font></div><font size="1"><span style="font-family:monospace,monospace"></span></font><br><br>-----------------------------------------------------------------------------------------------------------------------<br><div>Debug 3 log with Test3 results (secondary side, all SMs configured)), when there is error, slave goes to
PREOP+ERROR (test3log.txt attached). Here are the last few lines:<br></div><font size="1"><span style="font-family:monospace,monospace"><br>[91858.030437] EtherCAT DEBUG 0-0: Successfully configured PDO assignment of SM3.<br>[91858.030451] EtherCAT DEBUG 0-0: SM2: Addr 0x1800, Size 1, Ctrl 0x24, En 1<br>[91858.030457] EtherCAT DEBUG 0-0: SM3: Addr 0x1E00, Size 1, Ctrl 0x20, En 1<br>[91858.050861] EtherCAT DEBUG 0 0:0: FMMU: LogAddr 0x00000000, Size 1, PhysAddr 0x1E00, SM3, Dir in<br>[91858.050869] EtherCAT DEBUG 0 0:0: FMMU: LogAddr 0x00000001, Size 1, PhysAddr 0x1800, SM2, Dir out<br>[91858.110847] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).<br>[91858.131264] EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".<br>[91858.171002] EtherCAT 0-0: Acknowledged state PREOP.<br><br></span></font><br><br><br><br><br>*******<br><br></div>Test program is a simple, bare-bones version of the "user" example. Here is the important part the test program:<br><br><font size="1"><span style="font-family:monospace,monospace"><br>#define Beckhoff_EL6692 0x00000002, 0x1a243052<br>#define POS_6692 1 // for Test1, POS_6692=1; for Test2, POS_6692=0<br>#define DEFAULT_ENTRIES 0<br>#define SM0SM1 0 // for Test2, SM0SM1=0; for Test3, SM0SM1=1<br><br>#if DEFAULT_ENTRIES<br></span></font></div><font size="1"><span style="font-family:monospace,monospace">// Two seamingly invalid entries with Index/Subindex 0x0000:00<br></span></font></div><font size="1"><span style="font-family:monospace,monospace">// were manually removed<br></span></font><div><div><font size="1"><span style="font-family:monospace,monospace"> ec_pdo_entry_info_t el6692_pdo_default_entries[] = {<br> {0x10f4, 0x01, 2}, /* Sync Mode */<br> {0x1800, 0x09, 1}, /* TxPDO-Toggle */<br> {0x1800, 0x07, 1}, /* TxPDO-State */<br> {0x10f4, 0x0e, 1}, /* Control value update toggle */<br> {0x10f4, 0x0f, 1}, /* Time stamp update toggle */<br> {0x10f4, 0x10, 1}, /* External device not connected */<br> };<br>#endif<br><br>static unsigned int offs, bitpos, offs2, bitpos2;<br><br>ec_pdo_entry_reg_t regs[] = {<br> { 0, POS_6692, Beckhoff_EL6692, 0x7000, 0, &offs, &bitpos },<br> { 0, POS_6692, Beckhoff_EL6692, 0x6000, 0, &offs2, &bitpos2 },<br> { 0 },<br><br>};<br><br>ec_pdo_entry_info_t el6692_pdo_entries_Rx[] = {<br> {0x6000, 0x00, 8}, // to x1600, RxPDO<br>};<br>ec_pdo_entry_info_t el6692_pdo_entries_Tx[] = {<br> {0x7000, 0x00, 8}, // to x1a00, TxPDO<br>};<br>ec_pdo_info_t el6692_pdos[] = {<br> { 0x1600, 1, el6692_pdo_entries_Rx }, // RxPDO-Map<br> { 0x1a00, 1, el6692_pdo_entries_Tx }, // TxPDO-Map<br>#if DEFAULT_ENTRIES<br> { 0x1a01, 6, el6692_pdo_default_entries + 0 }, /* TxPDO-Map External Sync Compact */<br>#endif<br>};<br><br>ec_sync_info_t el6692_syncs[] = {<br>#if SM0SM1<br> { 0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE },<br> { 1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE },<br>#endif<br> { 2, EC_DIR_OUTPUT, 1, el6692_pdos + 0, EC_WD_DISABLE }, // --> RxPDO<br> { 3, EC_DIR_INPUT, 1, el6692_pdos + 1, EC_WD_DISABLE }, // --> TxPDO<br> { 0xff }<br>};<br></span></font><br><font size="1"><span style="font-family:monospace,monospace"><br>void cyclic_task()<br>{<br> // receive process data<br> ecrt_master_receive(master);<br> ecrt_domain_process(domain1);<br><br> counter++;<br><br> sleep(0);<br><br> // send process data<br> ecrt_domain_queue(domain1);<br> ecrt_master_send(master);<br>}<br><br>/****************************************************************************/<br><br>int main(int argc, char **argv)<br>{<br> ec_slave_config_t *sc;<br> struct sigaction sa;<br> struct itimerval tv;<br><br> master = ecrt_request_master(0);<br> if (!master)<br> return -1;<br><br> domain1 = ecrt_master_create_domain(master);<br> if (!domain1)<br> {<br> printf( "Could not create domain\n" );<br> return -1;<br> }<br> if (!(sc = ecrt_master_slave_config( master, 0, POS_6692, Beckhoff_EL6692)))<br> {<br> printf( "Failed to get slave configuration.\n" );<br> return -1;<br> }<br><br> if( ecrt_slave_config_pdos(sc, EC_END, el6692_syncs) )<br> {<br> printf( "Failed to configure PDOs for EL6692\n" );<br> return -1;<br> }<br><br> if (ecrt_domain_reg_pdo_entry_list(domain1, regs)) {<br> fprintf(stderr, "PDO entry registration failed!\n");<br> return -1;<br> }<br> printf("Activating master...\n");<br> if (ecrt_master_activate(master))<br> return -1;<br><br> if (!(domain1_pd = ecrt_domain_data(domain1))) {<br> return -1;<br> }<br><br>#if PRIORITY<br> pid_t pid = getpid();<br> if (setpriority(PRIO_PROCESS, pid, -19))<br> fprintf(stderr, "Warning: Failed to set priority: %s\n",<br> strerror(errno));<br>#endif<br><br> sa.sa_handler = signal_handler;<br> sigemptyset(&sa.sa_mask);<br> sa.sa_flags = 0;<br> if (sigaction(SIGALRM, &sa, 0)) {<br> fprintf(stderr, "Failed to install signal handler!\n");<br> return -1;<br> }<br><br> printf("Starting timer...\n");<br> tv.it_interval.tv_sec = 0;<br> tv.it_interval.tv_usec = 1000000 / FREQUENCY;<br> tv.it_value.tv_sec = 0;<br> tv.it_value.tv_usec = 1000;<br> if (setitimer(ITIMER_REAL, &tv, NULL)) {<br> fprintf(stderr, "Failed to start timer: %s\n", strerror(errno));<br> return 1;<br> }<br><br> printf("Started.\n");<br><br> int ix = 0;<br> while (1) {<br> pause();<br><br> while (sig_alarms != user_alarms)<br> {<br> cyclic_task();<br><br> sleep( 0 );<br> user_alarms++;<br> }<br> }<br><br> return 0;<br>}<br></span></font><br></div></div></div>