<html><head></head><body><div style="font-family: Verdana;font-size: 12.0px;"><div>
<div>Hi all,</div>
<div> </div>
<div>I'm relatively new to EtherCAT and EtherLab. My intended use is primarily closed loop feedback control with bandwidths up to, say, some tens of Hz. I have been successful in compiling all the software components and running the master on my test machine (Debian Wheezy with a packaged RT_PREEMPT Kernel + Matlab 2013a).</div>
<div> </div>
<div>I have now run into a problem with the "Discrete PID controller" block in Simulink which causes the following compile time error (copied from ML command window):</div>
<div> </div>
<div>### Building filter_test: /usr/local/MATLAB/R2013a/bin/glnxa64/gmake -f filter_test.mk EXT_MODE=0 EXTMODE_STATIC_ALLOC=0 EXTMODE_STATIC_ALLOC_SIZE=1000000 EXTMODE_TRANSPORT=0 MAT_FILE=0<br/>
CC filter_test_capi.o<br/>
In file included from filter_test_capi.c:19:0:<br/>
filter_test_private.h:36:2: error: #error "Code was generated for compiler with different sized ulong/long. Consider adjusting Emulation Hardware word size settings on the Hardware Implementation pane to match your compiler word sizes as defined in the compilers limits.h header file. Alternatively, you can select 'None' for Emulation Hardware and select the 'Enable portable word sizes' option for ERT based targets, this will disable the preprocessor word size checks."<br/>
gmake: *** [filter_test_capi.o] Error 1<br/>
### Build procedure for model: 'filter_test' aborted due to an error.<br/>
>></div>
<div> </div>
<div>My model consists of an EL3104 ADC block, the Discrete PID Controller block and an EL4134 DAC block. This error only shows up when there is a integral (and/or differential) gain present in the PID controller block. The model compiles without any issues if the controller only contains proportional gain.</div>
<div> </div>
<div>In the PID controller block, the data type of the "I parameter" is set to double, the type of "I product output" and "Integrator output" to "inherit via back propagation". Oddly enough, the error seems to depend on the setting of the sampling time. It only shows up if the sampling time in the Discrete PID Controller block is set to fractional number, e.g. 0.001, or to be inherited (i.e. -1). For (rather useless) positive integer values of the sampling time the model compiles without errors.</div>
<div> </div>
<div>I should mention that the same error pops up for other blocks, such as "Discrete Time Integral" and "Discrete Derivative" but also "Transfer Fcn First Order", for example.</div>
<div>Has anyone come across the same issue and knows how to fix this? Also, general hints or lessons learned on running PID controllers in EtherLab are more than welcome.</div>
<div> </div>
<div>Thank you very much for your help,</div>
<div> </div>
<div>best regards,</div>
<div> </div>
<div>Chris</div>
</div></div></body></html>