[etherlab-dev] Allowing slave to write to it's EEPROM registers

Erwin Burgstaller ethercat.berknapp at spamgourmet.com
Fri Jun 19 09:24:58 CEST 2009

* Tue, Jun 16, 2009 - 10:20:41 +0200, Florian Pose - fp at igh-essen.com:
> So you propose, that this bit (do you mean 0x501:1?) should be set every
> time when a slave goes to PREOP, after the SII has been read out by the
> master?

>From the documentation:

| EtherCAT controls the EEPROM interface if EEPROM configuration register 0x0500.0=0 and
| EEPROM PDI Access register 0x0501.0=0, otherwise PDI controls the EEPROM interface.
| In EEPROM emulation mode (IP Core with selected feature only), the PDI executes
| outstanding
| EEPROM commands. The PDI has access to some registers while the EEPROM Interface is busy.
|                               Table 54: Register EEPROM Configuration (0x0500)
|     Bit    Description                                           ECAT    PDI    Reset
| Value
|      0     EEPROM is assigned to                                 r/w     r/-    0
|            0: EtherCAT
|            1: PDI
|      1     Force PDI Access State:                               r/w     r/-    0
|            0: Do not change Bit 501.0
|            1: Reset Bit 501.0 to 0
|    7:2     Reserved                                              r/-     r/-    0
|                             Table 55: Register EEPROM PDI Access State (0x0501)
|     Bit    Description                                           ECAT    PDI    Reset
| Value
|      0     Access to EEPROM:                                     r/-     r/(w)  0
|            0: PDI releases EEPROM access
|            1: PDI has access to EEPROM
|    7:1     Reserved                                              r/-     r/-    0
| NOTE: r/(w): write access is only possible if 0x0500.0=1 and 0x0500.1=0.

So 0x0500.0 should be set to 1 and the slave could the set 0x0500.1 to
1, write it's data to the EEPROM and would set 0x0500.1 to 0 after that.
> The question is, when should the PDI access be disallowed again? The
> master accesses the SII only during slave scan and on 'ethercat
> sii_write', so perhaps resetting it just before that my be enough...

In some Beckhoff sample for slaves there's a comment:

| /* register 0x500.0 is set (should be written by the master before sending
|    the state transition request fro PREOP),we have access to the EPROM */

That would mean it should happen just before the transition to PREOP
(maybe after that SII-scan). With TwinCAT, the slave has (still) access
when the state transition to PREOP is requested. We think the access
will be disallowed when the slave is in PREOP state or on error/timeout

> The right place for allowing the PDI access is in
> master/fsm_slave_config.c, just before entering PREOP. It would have to
> be reset in master/fsm_slave_scan.c, just before reading the SII and in
> master/fsm_master.c, just before executing an SII request.

Should be OK too.


Erwin Burgstaller

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