[etherlab-users] Pdos and bit positions

[Erwin Burgstaller]

If I have something like this:

#define Beckhoff_EL2004 0x00000002, 0x07D43052
#define Beckhoff_EL2004_PDO_Output1 0x7000, 0x1
#define Beckhoff_EL2004_PDO_Output2 0x7010, 0x1
#define Beckhoff_EL2004_PDO_Output3 0x7020, 0x1
#define Beckhoff_EL2004_PDO_Output4 0x7030, 0x1

const static ec_pdo_entry_reg_t domain1_pdo_regs[] = {

   {0, 9,  Beckhoff_EL2004, Beckhoff_EL2004_PDO_Output1, &r_dig_out[0], &bit_pos[0]},
   {0, 9,  Beckhoff_EL2004, Beckhoff_EL2004_PDO_Output2, &r_dig_out[1], &bit_pos[1]},
   {0, 9,  Beckhoff_EL2004, Beckhoff_EL2004_PDO_Output3, &r_dig_out[2], &bit_pos[2]},
   {0, 9,  Beckhoff_EL2004, Beckhoff_EL2004_PDO_Output4, &r_dig_out[3], &bit_pos[3]},

   {}
};

Then after registration with:

ecrt_domain_reg_pdo_entry_list(domain1, domain1_pdo_regs)

I would have expected the following to work:

	for (i=0; i<4; i++)
	{
	   EC_WRITE_BIT(domain1_pd + r_dig_out[i], 0, blink ? 0x01 : 0x00);
	}

But only the first Output is 

By changing the write line to:

           EC_WRITE_BIT(domain1_pd + r_dig_out[i], i, blink ? 0x01 : 0x00);

It does the job.

Why? What are the other Pdos for, if I have to set the bit position anyway?

The listing looks like this:

$ ethercat pdos -s 9
SM0: PhysAddr 0x0f00, DefaultSize    0, ControlRegister 0x44, Enable 9
  RxPdo 0x1600 "Channel 1"
    Pdo entry 0x7000:01, 1 bit, "Output"
  RxPdo 0x1601 "Channel 2"
    Pdo entry 0x7010:01, 1 bit, "Output"
  RxPdo 0x1602 "Channel 3"
    Pdo entry 0x7020:01, 1 bit, "Output"
  RxPdo 0x1603 "Channel 4"
    Pdo entry 0x7030:01, 1 bit, "Output"

Btw., what are the RxPdo entries for?

Something differnt: When I write all 4 bits at once with EC_WRITE_U8,
will there be something overwritten?

The other way round: What do I read, if I call EC_READ_U8 on a 4-bit digital in?

Thanks,

 Erwin

-- 
Erwin Burgstaller