[etherlab-users] further investigations on NetX500 slave

[Phil Sutter]

Hi,

On Mon, Mar 03, 2008 at 11:01:38AM +0100, Florian Pose wrote:
> > What's strange here is my documentation states bytes 0x504-0x507 are for
> > specifying the EEPROM address to read/write from/to. But the function
> > mentioned above uses only two bytes for the address. Is this intended?
> 
> What kind of document do you mean? The EtherCAT Data Link Protocol
> Specification (IEC 61158-4-12 FDIS 08/07, p. 12078, table 50) states,
> that registers 504--505 shall contain the 16-bit word address.
> Registers 506--507 are not mentioned in the description of the SII
> interface.
> 
> Though: Figure 44 on page 12103 mentions the SII address as to be read
> from registers 0x0504--0x0507. Strange. I will be on the ETG technical
> committee meeting on Wednesday, and I will ask someone... ;-) Though I
> think, that this is deprecated.

The document I was talking about is the description of a lab exercise
for another hearing at my university. Though I'm not sure if I may
publish it, here it is: http://nwl.cc/~n0-1/SB2_EtherCAT.pdf :)
SII description starts at page 13, page 14 shows a table with the
questionable addresses.

> > Another thing is the EC_WRITE_U16 macro. Having a word offset of 0x40,
> > the resulting SII payload is:
> > | 80 01 40 00
> > which should be little endian, but actually isn't.
> 
> These are the bytes written to the registers 0x0502--0x0505, and the
> word address 0x0040 will be 0x40 0x00 in little endian, what makes your
> values perfectly valid.

Hmm. I'm starting to get confused. Doesn't little endian mean the least
significant bytes are the rightmost ones? Just like we write numbers:
(41152)_10 = (A0C0)_16 = (1010000011000000)_2
on a big endian system this would get:
(41152)_10 = (C0A0)_16 = (1100000010100000)_2
did I miss something?

> I still don't know, what's the problem with the netX slave. You say, the
> reading of the SII fails. Could you post the log messages with SII_DEBUG
> enabled?

Following the syslog-output after loading ec_master and ec_e1000 built
from an unmodified (besides SII_DEBUG) ethercat-1.4.0-pre-trunk-r1059:

| Mar  4 03:04:19 revan EtherCAT: Master driver 1.4.0-pre trunk r1059
| Mar  4 03:04:19 revan EtherCAT: 1 master waiting for devices.
| Mar  4 03:04:19 revan EtherCAT Intel(R) PRO/1000 Network Driver - version 7.3.20-k2-NAPI
| Mar  4 03:04:19 revan Copyright (c) 1999-2006 Intel Corporation.
| Mar  4 03:04:19 revan udev-net.sh: /etc/init.d/net.ecdbgm0: does not exist or is not executable
| Mar  4 03:04:19 revan ACPI: PCI Interrupt 0000:00:0a.0[A] -> GSI 18 (level, low) -> IRQ 20
| Mar  4 03:04:19 revan udev-net.sh: /etc/init.d/net.ecdbgb0: does not exist or is not executable
| Mar  4 03:04:19 revan e1000: 0000:00:0a.0: e1000_probe: (PCI:33MHz:32-bit) 00:0e:0c:d9:5f:4b
| Mar  4 03:04:19 revan EtherCAT: Accepting device 00:0E:0C:D9:5F:4B for master 0.
| Mar  4 03:04:19 revan EtherCAT: Starting master thread.
| Mar  4 03:04:19 revan e1000: ec0: e1000_probe: Intel(R) PRO/1000 Network Connection
| Mar  4 03:04:21 revan e1000: ec0: e1000_watchdog: NIC Link is Up 100 Mbps Full Duplex, Flow Control: RX
| Mar  4 03:04:21 revan EtherCAT: Link state changed to UP.
| Mar  4 03:04:21 revan EtherCAT: 1 slave responding.
| Mar  4 03:04:21 revan EtherCAT: Slave states: PREOP.
| Mar  4 03:04:21 revan EtherCAT: Scanning bus.
| Mar  4 03:04:21 revan EtherCAT DEBUG: reading SII data:
| Mar  4 03:04:21 revan EtherCAT DEBUG: 80 01 40 00
| Mar  4 03:04:21 revan EtherCAT DEBUG: checking SII read state:
| Mar  4 03:04:21 revan EtherCAT DEBUG: C0 20 40 00 00 00 80 01 01 00
| Mar  4 03:04:21 revan EtherCAT ERROR: SII: Error on last SII command!
| Mar  4 03:04:21 revan EtherCAT ERROR: Failed to read EEPROM size of slave 0.
| Mar  4 03:04:21 revan EtherCAT: Bus scanning completed in 0 ms.

> I have never had such a slave available for testing. What people told me
> up to now is:
> 
> - The slave does not support the LRW datagram. This is completely ok,
>   because the EtherCAT standard is designed for this. The master 1.4
>   will supported it.
> - The slave has no 'real' EEPROM, but an emulated one. This is ok too,
>   because the slave just has to implement the SII correctly. Though I
>   heard, that writing is not supported, which is a pity, if mandatory
>   SII data are missing.

Yes, I already found these two topics on the mailinglist. The funny
thing is, TwinCAT offers a button to upload the EEPROM data to the
device. When playing around with it, I could at least save two different
versions of the EEPROM to file. I posted the bigger one already, this is
the small one:

| 0000000 0000 0000 0000 0000 0000 0000 0000 0000
| 0000010 0044 0000 656e 7874 0001 0003 0000 0000
| 0000020 ffff ffff ffff ffff ffff ffff ffff ffff
| *
| 0000080

I tried writing both images into the slave's EEPROM using sysfs, but it
failed complaining an incorrect size. Though I suspect my other problems
as the first reason for that.

> > PS: is there any way to getting information about EtherCAT (especially
> > SII structure) without becoming an ETG member?
> 
> AFAIK no, but becoming an ETG member is easy and free of charge... ;-)

Hey, good news! The last state of my research was the offer to buy
DS/IEC/PAS 62407 for 174 USD from store.ihs.com.

Greetings, Phil