[etherlab-users] Slave register access

[William Montgomery]

Florian Pose wrote:
> On Wed, Nov 05, 2008 at 09:11:18AM -0500, William Montgomery wrote:
>   
>> I am a newbie with respect to ethercat so I am not sure of the best
>> way to do this.  I would like to create a sync pulse on the slave for
>> each write to the slave.  I have found that I can write to a register
>> on the slave controller to cause this pulse.  I can modify the eeprom
>> on the slave to add another sync manager and pdo for this but was
>> unsure if I should use mailbox or buffer method to access the
>> registers.  After further reading, I thought that the whole PDO/sync
>> mgr approach might not be necessary and that I could bypass that
>> mechanism with a more direct method.
>>     
>
> This is indeed the usual way. Create a sync manager configuration (in
> buffered mode) with at least one Pdo containing a Pdo entry. You can
> check the Pdo configuration that the master read by calling 'ethercat
> pdos'.
>
> Then you can register that Pdo entry via the API and exchange it
> cyclically (like in the minimal example), then the sync pulse should be
> generated on every access.
>
>   
I followed your suggestions but I do not think the slave controller ASIC 
(Beckhoff ET1100) handles the register access via sync manager in the 
expected way.  I am not getting any sync pulses.

I do get the following from "ethercat pdos":

SM0: PhysAddr 0x1020, DefaultSize    4, ControlRegister 0x44, Enable 9
  RxPdo 0x1a00 "Slave Inputs from Master"
    Pdo entry 0x3101:01, 16 bit, "Servo AO 16 bit"
    Pdo entry 0x3102:01, 16 bit, "CMD WORD 16 bit"
SM1: PhysAddr 0x1040, DefaultSize   10, ControlRegister 0x40, Enable 9
  TxPdo 0x1600 "Slave Outputs to Master"
    Pdo entry 0x3001:01, 32 bit, "Encoder 32 bit"
    Pdo entry 0x3002:01, 16 bit, "Force AI 16 bit"
    Pdo entry 0x3003:01, 16 bit, "POT AI 16 bit"
    Pdo entry 0x3004:01, 16 bit, "DAQ AI 16 bit"
SM2: PhysAddr 0x0980, DefaultSize    2, ControlRegister 0x44, Enable 9
  RxPdo 0x1a01 "Slave Inputs from Master"
    Pdo entry 0x3103:01, 16 bit, "SYNC Out Ctl"


This is a Custom IO board I am developing that uses the Beckhoff 
FB1111-0140 slave board.  As you can see, SM2 maps to the register space 
that I need to write to in order to generate the sync pulse.  I am using 
the cyclic exchange per the examples and I can successfully communicate 
with the other Pdo entries but not the sync out ctl regs.  I was reading 
in the ET1100 hardware manual about how the sync manager works in buffer 
mode.  An example was shown that indicates 3 buffers are used and 
allocated adjacent to the physical address specified.  This is probably 
not applicable to register space and I think the ET1100 may just be 
ignoring this sync manager since I have tried to map it to register space.

Regards,
Wm