[etherlab-users] EL5101 with DC
Peter van Knippenbergh
peter.van.knippenbergh at sioux.eu
Wed Oct 28 09:26:13 CET 2009
I want to use EL5101 with distributed clocks with IGH master revision 1824.
My slave configuration is Slave 0 : EK1100, slave 1 - 8 : EL2008 , slave 9 :
EK1100, slave 10 : EL5101, SLAVE 11 : EL4032 (all beckhoff modules
To enable the dc for the EL5101 slave, I use the following line in my code
ecrt_slave_config_dc(sc, 0x0320, 250000, 0, 250000 , 0);
When I add this line to my application I got the following dmesg
The exact error message (debuglevel = 1, with dmesg)
[ 1134.835273] EtherCAT DEBUG: Slave 10: Setting DC cycle times to 250000 /
0.
[ 1134.835774] EtherCAT DEBUG: app_start_time=17500059273709551616
[ 1134.835777] EtherCAT DEBUG: start_time=17500059273809551616
[ 1134.835778] EtherCAT DEBUG: cycle_time=250000
[ 1134.835780] EtherCAT DEBUG: shift_time=0
[ 1134.835782] EtherCAT DEBUG: remainder=0
[ 1134.835783] EtherCAT DEBUG: start=17500059273809801616
[ 1134.835786] EtherCAT DEBUG: Slave 10: Setting DC cyclic operation start
time to 17500059273809801616.
[ 1134.836273] EtherCAT DEBUG: Slave 10: Setting DC AssignActivate to
0x0320.
[ 1134.838774] EtherCAT ERROR: Failed to set SAFEOP state, slave 10 refused
state change (PREOP + ERROR).
[ 1134.839274] EtherCAT ERROR: AL status message 0x0030: "Invalid DC SYNCH
configuration".
[ 1134.840272] EtherCAT: Acknowledged state PREOP on slave 10.
[ 1134.843414] EtherCAT DEBUG: Changing state of slave 0 from PREOP to OP.
And I got the 0x320 from xml that I generated with twincat
<DC>
<ReferenceClock>1</ReferenceClock>
<CycleTime0>4000000</CycleTime0>
<CycleTime1>0</CycleTime1>
<ShiftTime>0</ShiftTime>
<OpMode>
<Name>Synchron</Name>
<Desc>Synchron</Desc>
<AssignActivate>#x0</AssignActivate>
<CycleTimeSync0 Factor="0">0</CycleTimeSync0>
<ShiftTimeSync0>0</ShiftTimeSync0>
<CycleTimeSync1 Factor="1">0</CycleTimeSync1>
<ShiftTimeSync1>0</ShiftTimeSync1>
</OpMode>
<OpMode Selected="1">
<Name>DC</Name>
<Desc>DC</Desc>
<AssignActivate>#x320</AssignActivate>
<CycleTimeSync0 Factor="1">0</CycleTimeSync0>
<ShiftTimeSync0>0</ShiftTimeSync0>
<CycleTimeSync1 Factor="1">0</CycleTimeSync1>
<ShiftTimeSync1>0</ShiftTimeSync1>
</OpMode>
<OpMode>
<Name>DCIN</Name>
<Desc>DCIN</Desc>
<AssignActivate>#x320</AssignActivate>
<CycleTimeSync0 Factor="1">0</CycleTimeSync0>
<ShiftTimeSync0>0</ShiftTimeSync0>
<CycleTimeSync1 Factor="1">0</CycleTimeSync1>
<ShiftTimeSync1>0</ShiftTimeSync1>
</OpMode>
</DC>
So I started and dumped registers and objects while my application is
running (10 0:10 PREOP E EL5101 1K. Inc. Encoder 5V)
./ethercat upload -p 10 -t int16 0x1c32 0x01 : Sync mode
0x0001 1
./ethercat upload -p 10 -t int32 0x1c32 0x02 : Cycle time
0x0003d090 250000
./ethercat upload -p 10 -t int32 0x1c32 0x03 : Shift time
0x00000000 0
./ethercat upload -p 10 -t int16 0x1c32 0x04 : Sync mode supported
0xc007 -16377
./ethercat upload -p 10 -t int32 0x1c32 0x05 : Minimum cycle time
0x000101d0 66000
./ethercat upload -p 10 -t int32 0x1c32 0x06 : Calc and copy time
0x00000000 0
./ethercat upload -p 10 -t int16 0x1c32 0x08 : Command
0x0000 0
./ethercat upload -p 10 -t int32 0x1c32 0x09 : Delay time
0x00000000 0
./ethercat upload -p 10 -t int16 0x1c32 0x0B : SM event missed counter
0x0000 0
./ethercat upload -p 10 -t int16 0x1c32 0x0C : Cycle exceeded counter
0x0000 0
./ethercat upload -p 10 -t int16 0x1c32 0x0D : Shift too short counter
0x0000 0
./ethercat upload -p 10 -t int8 0x1c32 0x20 : Sync error
0x00 0 0x0320 800
./ethercat reg_read -p 10 REG_DCTIME0 = 0x0900,32
0x9982203c -1719525316
./ethercat reg_read -p 10 REG_DCTIME1 = 0x0904,32
0x99822172 -1719525006
./ethercat reg_read -p 10 REG_DCTIME2 = 0x0908,32
0x00000000 0 ./ethercat reg_read -p 10 REG_DCSYSTIME = 0x0910,64
0xf2dcb345afa7a8c8 -946684709773530936
./ethercat reg_read -p 10 REG_DCSOF = 0x0918,64
0x000000009982203c 2575441980
./ethercat reg_read -p 10 REG_DCSYSOFFSET = 0x0920,64
0xf2dcaf51da7b1679 -946689055561935239
./ethercat reg_read -p 10 REG_DCSYSDELAY = 0x0928,32
0x00000bb3 2995
./ethercat reg_read -p 10 REG_DCSYSDIFF = 0x092C,32
0x00000002 2
./ethercat reg_read -p 10 REG_DCSPEEDCNT = 0x0930,16
0x1000 4096
./ethercat reg_read -p 10 REG_DCTIMEFILT = 0x0934,16
0x0c04 3076
./ethercat reg_read -p 10 REG_DCCUC = 0x0980,8
0x20 32
./ethercat reg_read -p 10 REG_DCSYNCACT = 0x0981,8
0x03 3
./ethercat reg_read -p 10 REG_DCSTART0 = 0x0990,64
0xf2dcb345b72e8db0 -946684709647250000
./ethercat reg_read -p 10 REG_DCCYCLE0 = 0x09A0,32
0x0003d090 250000
./ethercat reg_read -p 10 REG_DCCYCLE1 = 0x09A4, 32
0x0003d090 250000
./ethercat reg_read -p 10 0x0982 Pulse lenght of Sync signales , 16
0x00000000 0
./ethercat reg_read -p 10 0x098E SYNC0 status, 8
0x01 1
./ethercat reg_read -p 10 0x098F SYNC1 status, 8
0x00 0
$ ./ethercat reg_read -p 10 0x0980 -t int16
0x0320 800
$ ./ethercat reg_read -p 10 0x0980 -t int8
0x20 32
I saw in the IGH driver (revision 1824) that 2 bytes are written to a 1 byte
register
void ec_fsm_slave_config_enter_dc_clear_assign(
ec_fsm_slave_config_t *fsm /**< slave state machine */
)
{
.......
ec_datagram_fpwr(datagram, slave->station_address, 0x0980, 2); ........
}
Is that correct ??
But my main issue, how can I enable DC on the EL5101 with the IGH master.
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