[etherlab-users] Theoretical DC question.

[Raz Ben Yehuda]

On Mon, 2012-07-23 at 09:46 +0200, Bilko AS, Oguz Dilmac wrote:
> Hi,
> 
> I also wonder, how the synchronisations is made.
> 
> I know that, master should send ARMW or FRMW commands to read system 
> time from the first DC slave (reference clock) and write to the rest of 
> the slaves this system time. Finally the time differences of the slaves 
> in the register 0x92C should be low enough.
> 
> I tested DC with only one DC capable slave. So I assume this slave is 
> also the reference clock. Then I'd expect 0x92C would be always zero.
> But when I check the synchrony as suggested in users manual with 
> following command, I saw that the system time is oscilating very much!
> watch -n0 "ethercat reg_read -p0 -tsm32 0x92c"
> Gradually it closes to zero but this takes a long time.
> 
> If the first slave is the DC reference clock, then why 0x92C is not zero 
> all the time?
> 
> Best regards,
> Oguz.
>From what I have been reading, never expect them to drop to zero. 
The frequencies are slightly different between the clocks.
> 
> 22.07.2012 13:31 tarihinde, Raz Ben Yehuda yazdı:
> > How do we make the master transmit packet in the right time ?
> >
> > Is is said in the etherlab book that all slaves are fixing the local
> > clocks according to a caluclated error.
> > 1. who writes to the system time register ? is it the first slave or the
> > master ? I noticed that it possible to that in the master but this is
> > not the correct behavior as i understand.
> >
> > 2. if a master needs to transmit the N-th packet so that i will be
> > processed in the N-th tick of the reference (first) slave, how do i do
> > that ? how do i know how much time BEFORE the n-th tick to transmit the
> > packet ?
> >
> > thank you
> >
> 

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