[etherlab-users] LRW datagram on TI-ICE development board

[Gianluca Medini]

Hi all,
I'm playing with IGH on a Texas instruments ICE development kit.
The process image has input (5 bytes) and outputs (7 bytes) , so the 
master configures FMMU in order to have a single datagram LRW.
The data size of the LRW is 12 bytes, although should optimize to 7; 
I've analyzed the wireshark capture of  twincat on the same hardware and 
it make this optimization (an image of 7 bytes).
With this not optimized configuration of FMMU the boards doesn't work (I 
think is problem on the ESC controller, I've checked this), however I 
was wondering if making this optimization could be a desiderable behaviour.
There is some compilation switch / parameter on IGH  that  can modify 
this behaviour ?

Regards
Gianluca Medini

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Dott. Gianluca Medini
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