[etherlab-users] Bit offset + write macros

[Christian Gieseler]

I have a question concerning the write macros that are offered by the API in ecrt.h.

My example configuration is shown below. Slave0 and Slave1 are free configurable slaves (Beckhoff FB1111-0140 Module). The problem is that that all pdo entries of the RxPdo 0x1601 are shiftet one bit due to RxPdo 0x1600. As far as i see there is no possiblity to write the Data to the right position using the offered read and write macros, even if i have the bit_position available. 
I can solve this by not using the macros and writing the data by using my own bitshifting function. 
But i am wondering if there is a reason that the macros don´t offer the possiblitiy to get allong with this problem. Or is it a slave configuration fault and the RxPdo 0x1600 has to be "padded" like it is done with the TxPdo 0x1a01 of Slave 3?

Regards 
Christian

=== Slave 0 ===
SM0: PhysAddr 0x1000, DefaultSize  512, ControlRegister 0x26, Enable 1
SM1: PhysAddr 0x1200, DefaultSize  512, ControlRegister 0x22, Enable 1
SM2: PhysAddr 0x1400, DefaultSize    6, ControlRegister 0x24, Enable 1
  RxPdo 0x1600 ""
    Pdo entry 0x6000:00,  1 bit, ""
  RxPdo 0x1601 ""
    Pdo entry 0x6001:01,  8 bit, ""
    Pdo entry 0x6001:02,  8 bit, ""
    Pdo entry 0x6001:03,  8 bit, ""
    Pdo entry 0x6001:04,  8 bit, ""
    Pdo entry 0x6001:05,  8 bit, ""
    
SM3: PhysAddr 0x144e, DefaultSize   5, ControlRegister 0x20, Enable 1
  TxPdo 0x1a00 ""
    Pdo entry 0x7000:01,  8 bit, ""
    Pdo entry 0x7000:02,  8 bit, ""
    Pdo entry 0x7000:03,  8 bit, ""
    Pdo entry 0x7000:04,  8 bit, ""
    Pdo entry 0x7000:05,  8 bit, ""
    
=== Slave 1 ===
SM0: PhysAddr 0x1000, DefaultSize  512, ControlRegister 0x26, Enable 1
SM1: PhysAddr 0x1200, DefaultSize  512, ControlRegister 0x22, Enable 1
SM2: PhysAddr 0x1401, DefaultSize   6, ControlRegister 0x24, Enable 1
  RxPdo 0x1600 ""
    Pdo entry 0x6000:01,  8 bit, ""
    Pdo entry 0x6000:02,  8 bit, ""
    Pdo entry 0x6000:03,  8 bit, ""
    Pdo entry 0x6000:04,  8 bit, ""
    Pdo entry 0x6000:05,  8 bit, ""
    Pdo entry 0x6000:06,  1 bit, ""
=== Slave 2 ===
=== Slave 3 ===
SM0: PhysAddr 0x1000, DefaultSize    0, ControlRegister 0x22, Enable 0
  TxPdo 0x1a00 "Channel 1"
    Pdo entry 0x6000:01,  1 bit, "Input"
  TxPdo 0x1a01 "Channel 2"
    Pdo entry 0x6000:02,  1 bit, "Input"
    Pdo entry 0x0000:00,  6 bit, ""
  TxPdo 0x1a02 "Reserved"
SM1: PhysAddr 0x09ae, DefaultSize    0, ControlRegister 0x00, Enable 4
  TxPdo 0x1a13 "Latch"
    Pdo entry 0x1d09:ae,  8 bit, "Status1"
    Pdo entry 0x1d09:af,  8 bit, "Status2"
    Pdo entry 0x1d09:b0, 64 bit, "LatchPos1"
    Pdo entry 0x1d09:b8, 64 bit, "LatchNeg1"
    Pdo entry 0x1d09:c0, 64 bit, "LatchPos2"
    Pdo entry 0x1d09:c8, 64 bit, "LatchNeg2"
SM2: PhysAddr 0x0910, DefaultSize    0, ControlRegister 0x00, Enable 4
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