[etherlab-users] Arrival of large amounts of data

[Shahbaz Yousefi]

> What is your cycletime?
Say 40ms

> Do you need all frames with the same cycle time?
Let's say yes

> The master splits the data automatically or via predefined domains in
several frames?
Again, let's say it's only 1 domain

> The master use the diffent buffers of the network card automatically.
Alright, so now I know that the amount of data is bound by network card's
buffers.

> But note, to have a good multiframe configuartion you should use a real
stupid card (Realtek) not the Intel stuff.
Yeah, we read this on another thread, but thanks for emphasizing :)

> You have the possibility to use more than 1 master to reduce your
bandwidth load for the network card.
Also a good point. I was thinking about it when I wrote the question. The
question however was more to understand better the internals of how EtherCAT
master works. In reality, we do have multiple domains and if we have to,
multiple masters. With multiple masters though, it is as if we have two
completely separate networks and I just wanted to know how scalable _one_
network could get which I got it now.

> Also you have to check the bandwidth of the PCI bus for this
configuration, PCI Express is much better.
I don't understand this one though. Say the task period is 40ms and the time
it takes for the ethernet frames to arrive back at the network card is 4ms.
This way, while I am sleeping, all the many ethernet frames return to the
card. So my PCI bus being fast or slow has no effect on whether my network
card's buffer gets full or not.

> I think you are using oversampling slaves, or?
Not really, I just have many of them.

> The master does not poll. You have to to prepare a setup like
> -wakeup
> - process frames (X times)
> - calculate
> - write frames (X times)
> -sleep!!!!!
Yes that's what we are doing.

> - You have to compare your frame cycle time, given by the physics and
number of frames, your calculation time and your process cycle time. The
cycle time should be minimal 2 times greater than the sum of the other
times.
In fact this time is much smaller than the speed at which the hardware
generates the data, so we have no problem defining the cycle time and there
is a big amount of sleep.

> Best regards
To you too :D

> Andreas
Shahbaz
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