[etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

[Gavin Lambert]

Are you using the generic ethernet driver or one of the provided EtherCAT-enabled drivers?  What HZ is your kernel using?

 

On standard x86 hardware, you’re unlikely to get much better than 4 ms cycle rates even on Linux+PREEMPT_RT if you’re using the generic driver.  Since you’re using more cut-down hardware, it wouldn’t surprise me if this were more limited.

 

From: etherlab-users [mailto:etherlab-users-bounces at etherlab.org] On Behalf Of Brian Cheng
Sent: Tuesday, 17 February 2015 13:44
To: etherlab-users at etherlab.org
Subject: [etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

 

Hi,

Does anyone could run short cycle(<<1ms) well using Igh EtherCAT master for linux-RT of Cyclone V (ARM CortexA9 925Mhz) ?

I got the linux-socfpga.git for downloading Linux-3.10-ltsi-rt.
I already put the EtherCAT module & application on the Linux-RT Helio board for Cyclone V.
It could run well as communication cycle as 10 ms.

And the Ethernet port will block when  using 1ms transmit rate.
SKIPPED datagram always occur.
It seems that the delay of ethernet transmit/receive function is too long.


Has anyone already verify the situation or anyone could point out the delay issue?



Thanks a lot.

          Brian              

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