[etherlab-users] SKIPPED datagram using Igh EtherCAT master porting for Linux OS on CyconeV SoC

[Brian Cheng]

Hi,

Does anyone could run short cycle(<<1ms) well using Igh EtherCAT master for
linux-RT of Cyclone V (ARM CortexA9 925Mhz) ?

I got the linux-socfpga.git for downloading Linux-3.10-ltsi-rt.
I already put the EtherCAT module & application on the Linux-RT Helio board
for Cyclone V.
It could run well as communication cycle as 10 ms.

And the Ethernet port will block when  using 1ms transmit rate.
SKIPPED datagram always occur.
It seems that the delay of ethernet transmit/receive function is too long.

Has anyone already verify the situation or anyone could point out the delay
issue?

Thanks a lot.

          Brian
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