[etherlab-users] Lenze Vector preop eeprom error

Janssen Matthias mjanssen at seepex.com
Wed Mar 28 11:27:31 CEST 2018 

Hi Guys,

We are currently facing problems getting a Lenze inverter 8200 vector working with the IgH EtherCat master.
The inverter is fitted with a communication module Lenze EMF2192IB for EtherCat support. Originally, the module identifies as 33S2192I-Default, containing only dummy objects.
We could get it working with TwinCAT and the corresponding ESI file, it is then found as 'Inverter 8200 vector'.
Our next step was to generate an SII-binary from the ESI file using TwinCAT, and then write it to the SII using the IgH master, according to http://etherlab.org/de/ethercat/faq.php

Now it is recognized as 'Inverter 8200 vector' by the master, but it still fails to get into the PREOP state. The AL status is 0x51(EEPROM error).
When requesting PREOP state, we find this in the syslog:

[ 3576.220819] EtherCAT 0: Master debug level set to 1.
[ 3580.775050] EtherCAT DEBUG 0-8: Changing state from INIT to PREOP.
[ 3580.775076] EtherCAT DEBUG 0-8: Configuring...
[ 3580.775511] EtherCAT DEBUG 0-8: Now in INIT.
[ 3580.775524] EtherCAT DEBUG 0-8: Clearing FMMU configurations...
[ 3580.775772] EtherCAT DEBUG 0-8: Clearing sync manager configurations...
[ 3580.776012] EtherCAT DEBUG 0-8: Clearing DC assignment...
[ 3580.776261] EtherCAT DEBUG 0-8: Configuring mailbox sync managers...
[ 3580.776279] EtherCAT DEBUG 0-8: SM0: Addr 0x1000, Size 256, Ctrl 0x26, En 1
[ 3580.776295] EtherCAT DEBUG 0-8: SM1: Addr 0x1100, Size 256, Ctrl 0x22, En 1
[ 3580.777374] EtherCAT ERROR 0-8: Failed to set PREOP state, slave refused state change (INIT + ERROR).
[ 3580.777646] EtherCAT ERROR 0-8: AL status message 0x0051: "EEPROM Error".
[ 3580.777998] EtherCAT 0-8: Acknowledged state INIT.

The category data seems to have been written to the SII. Reading out the SII data returns:

$ ethercat sii_read -p8 -v
SII Area:
  05 0c 03 0e 98 3a 00 00 00 00 00 00 00 00 1b 00
  3b 00 00 00 64 79 4e 01 01 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 10 f4 00 f4 10 f4 00
  00 10 00 01 00 11 00 01 0c 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 0f 00 01 00
SII Category 0x000a (STRINGS), 66 words
  0d 14 49 6e 76 65 72 74 65 72 20 38 32 30 30 20
  76 65 63 74 6f 72 06 44 72 69 76 65 73 05 44 63
  4f 66 66 09 49 4f 20 49 6e 70 75 74 73 0c 54 78
  50 44 4f 20 54 6f 67 67 6c 65 0b 54 78 50 44 4f
  20 53 74 61 74 65 07 49 6e 70 75 74 30 31 07 49
  6e 70 75 74 30 32 07 49 6e 70 75 74 30 33 0a 49
  4f 20 4f 75 74 70 75 74 73 08 4f 75 74 70 75 74
  30 31 08 4f 75 74 70 75 74 30 32 08 4f 75 74 70
  75 74 30 33
SII Category 0x001e (General), 16 words
  02 00 01 01 01 2b 01 00 00 00 00 04 00 00 02 00
  11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
SII Category 0x0028 (FMMU), 2 words
  01 02 03 ff
SII Category 0x0029 (SyncM), 16 words
  00 10 00 01 26 00 01 01 00 11 00 01 22 00 01 02
  00 12 06 00 24 00 01 03 00 19 08 00 20 00 01 04
SII Category 0x0032 (TXPDO), 28 words
  00 1a 06 03 00 04 01 00 00 00 00 00 00 0e 00 00
  00 18 09 05 01 01 00 00 00 18 07 06 01 01 00 00
  e0 58 01 07 03 10 00 00 e0 58 02 08 03 10 00 00
  e0 58 03 09 03 10 00 00
SII Category 0x0033 (RXPDO), 16 words
  00 16 03 02 00 0a 01 00 e1 58 01 0b 03 10 00 00
  e1 58 02 0c 03 10 00 00 e1 58 03 0d 03 10 00 00
SII Category 0x003c (DC), 12 words
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 03 00 00 00 00 00

A short test showed that it is still working with TwinCAT, regardless of the different SII data.

The slave information output by the master:

$ ethercat slaves -p8 -v
=== Master 0, Slave 8 ===
Device: Main
State: INIT
Flag: E
Identity:
  Vendor Id:       0x0000003b
  Product code:    0x014e7964
  Revision number: 0x00000001
  Serial number:   0x00000000
DL information:
  FMMU bit operation: no
  Distributed clocks: yes, 64 bit
  DC system time transmission delay: 2570 ns
Port  Type  Link  Loop    Signal  NextSlave  RxTime [ns]  Diff [ns]   NextDc [ns]
   0  MII   up    open    yes             0   3050637146           0         550
   1  MII   down  closed  no              -            -           -           -
   2  N/A   down  closed  no              -            -           -           -
   3  N/A   down  closed  no              -            -           -           -
Mailboxes:
  Bootstrap RX: 0x1000/244, TX: 0x10f4/244
  Standard  RX: 0x1000/256, TX: 0x1100/256
  Supported protocols: CoE, FoE
General:
  Group: Drives
  Image name:
  Order number: Inverter 8200 vector
  Device name: Inverter 8200 vector
  CoE details:
    Enable SDO: yes
    Enable SDO Info: yes
    Enable PDO Assign: no
    Enable PDO Configuration: yes
    Enable Upload at startup: no
    Enable SDO complete access: yes
  Flags:
    Enable SafeOp: no
    Enable notLRW: no
  Current consumption: 0 mA

What hits the eye is that distributed clock is being indicated as supported, which is wrong, according to the corresponding entry in the ESI file:

<Dc>
                <OpMode>
                               <Name>DcOff</Name>
                               <Desc>DC unused</Desc>
                               <AssignActivate>#x0</AssignActivate>
                               <CycleTimeSync0 Factor="0">0</CycleTimeSync0>
                               <ShiftTimeSync0>0</ShiftTimeSync0>
                               <CycleTimeSync1 Factor="1">0</CycleTimeSync1>
                               <ShiftTimeSync1>0</ShiftTimeSync1>
                </OpMode>
</Dc>


Thanks in advance for any idea that could help with the problem.

Best regards

Matthias Janßen
Electrical Engineering


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